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LMT035DNJFWD
LCD Module User Manual
Prepared by:
Checked by:
Approved by:
Lin Yong Jie
Date: 2017-05-19
Date:
Date:
Rev. Descriptions
Release Date
0.1
Preliminary New release
2017-05-19
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Document Name: LMT035DNJFWD-Manual-Rev0.1
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Table of Content
1. Basic Specifications ................................................................................................................... 3
1.1 Block Diagram ................................................................................................................................................................ 3
1.2 Terminal Functions ......................................................................................................................................................... 4
2. Absolute Maximum Ratings ...................................................................................................... 5
3. Electrical Characteristics .......................................................................................................... 5
3.1 DC Characteristics ......................................................................................................................................................... 5
3.2 LED Backlight Circuit Characteristics ............................................................................................................................. 5
4. AC Characteristics ..................................................................................................................... 5
4.1 DBI Type B ..................................................................................................................................................................... 6
4.2 3-Line SPI Interface Timing Characteristic ................................................................................................................... 11
4.3 4-Line SPI Interface Timing Characteristic ................................................................................................................... 12
4.4 DPI Interface ................................................................................................................................................................ 13
4.5 Power ON/OFF Sequence............................................................................................................................................ 17
4.6 Reset timing ................................................................................................................................................................. 19
5 . Optical Characteristics ............................................................................................................ 19
6. Design and Handling Precaution ............................................................................................ 21
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1. Basic Specifications
Screen Size(Diagonal) :
3.5”
Color Depth:
65K/262K Color
Number of dots :
320(RGB)x480
Active Area :
48.96x73.44
Dot Pitch :
0.153x0.153mm
Display Technology :
a-Si TFT active matrix
Display Mode :
Transmissive With Normally white
Pixel Configuration :
RGB Vertical Stripe
Viewing Direction :
12H (*1) (gray scale inverse)
6H (*2)
Polarizer Surface Treatment:
HC
Backlight Type:
LEDs
Outline Dimension :
55.26x 84.69 x 2.2 mm
(exclude FPC , see dwg for details)
Operating Temperature :
-20 ~ +70°C (No Condensation)
Storage Temperature :
-30 ~ +80°C (No Condensation)
Note:
*1. For saturated color display content (eg. pure-red, pure-green, pure-blue or pure-colors-combinations).
*2. For “color scales” display content.
*3. Color tone may slightly change by temperature and driving condition.
1.1 Block Diagram
BLA, BLK1~6
Backlight Circuit
TFT Panel
320(RGB) × 480
VDD,IOVDD
VSS
/WR(SCL),/RD,RS,D0~D17
ILI9488 or equivalent
/CS, /RST, RS,TE,LCM_ID,IM0~2
SDI,SDO,DE,DCLK,VS,HS
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1.2 Terminal Functions
PIN
Pin No.
Name
I/O
Descriptions
1
TE
Output
Output a frame head pulse signal
If no used, please open this pin
2
VSS
Power NegAtive power supply,0V
3
DE
Input
Data enable signal in RGB mode
If no used, please fix this pin at VSS level
4
DCLK
Input
Pixel clock signal in RGB mode
If no used, please connect this pin to VSS
5
VS
Input
Vertical sync. signal in RGB mode
If no used, please connect this pin to VSS
6
VSS
Power Ground
7
HS
Input
Horizontal sync, signal in RGB mode
If no used, please connect this pin to VSS
8
IM0
Input
MPU system interface mode select
9
IM1
Input
MPU system interface mode select
10
IM2
Input
MPU system interface mode select
11
IOVDD
Power IO Positive Power
12
VDD
Power Positive power supply
Serial data in/out pin in DBI Type C 9bit mode
13
SDI
I/O
Serial data input pin in DBI Type B 8bit mode
If no used, please connect this pin to vss
14
SDO
Output
Serial data output pin
If no used, leave this pin open
15
D17
I/O
:
:
:
Data Bus
32
D0
I/O
Reset signal
33
/RST
Input
/RST = L, Initialization is executed
/RST = H, Normal running.
34
/RD
Input
Read strobe signal
If no used, please connect this pin to IOVDD
(WR) Write data enable pin in DBI Type B
35
/WR(SCL)
Input
(SCL) Write data enable pin in DBI Type C
If no used, please connect this pin to IOVDD
36
RS
Input
Data/command selection pin
If no used, please connect this pin to IOVDD
37
/CS
Input
Chip select signal
If no used, please connect this pin to IOVDD
38
BLK6
Power
:
:
:
LEDS CATHODE
43
BLK1
Power
44
BLA
Power LED ANODE
45
LCM_ID
Output Customer requirement : 1.8V
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2. Absolute Maximum Ratings
Items
Symbol
Min.
Max.
Unit
Condition
Power Voltage
VDD
-0.3
+3.3
V
V SS = 0V
Input Voltage
V IN
-0.3
+3.3
V
V SS = 0V
Operating Temperature
T OP
-20
+70
 C
No Condensation
Storage Temperature
T ST
-30
+80
 C
No Condensation
Cautions:
Any Stresses exceeding the Absolute Maximum Ratings may cause substantial damage to the device. Functional
operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure
to extreme conditions may affect device reliability.
3. Electrical Characteristics
3.1 DC Characteristics
V SS =0V, T OP =25  C
Items
Symbol
MIN.
TYP.
MAX.
Unit Condition /
Application Pin
Operating Voltage
VDD
2.65
3.0
3.3
V
VDD,IOVDD
Input High Voltage
V IH
0.7xV DD
-
V DD
V
TE 、 DE 、 DCLK 、
VS 、 HS 、 IM0~2 、
SDI 、 SDO 、
Input Low Voltage
V IL
-0.3
-
0.3xV DD
V
D0~D17 、 /RST 、
/RD 、 WR(SCL) 、
RS 、 /CS 、 LCM_ID
Operating Current
I DD
-
TBD
-
mA VDD (*1)
Note: *1. VDD=3.0V
3.2 LED Backlight Circuit Characteristics
BLK(1~6)=0V, I BLA =120mA, T OP =25  C
Items
Symbol
MIN.
TYP.
MAX.
Unit
Applicable Pin
Forward Voltage
BLA
-
3.2
-
V
BLA
Forward Current
I BLA
-
120
-
mA
BLA
Cautions:
Exceeding the recommended driving current could cause substantial damage to the backlight and shorten its lifetime.
BLA
BLK1
:
BLK6
No. of LEDs = 6pcs
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4. AC Characteristics
4.1 DBI Type B
4.1.1 DBI Type B Timing Characteristic
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4.1.2 DBI Type B Data Bus
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4.2 3-Line SPI Interface Timing Characteristic
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4.3 4-Line SPI Interface Timing Characteristic
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4.4 DPI Interface
4.4.1 DPI Interface Characteristic
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4.4.2 DPI Interface pixel format
The Pixel clock (DCLK) runs all the time without stop. It is used to enter VS, HS, DE and D[17: 0] states
when there is a rising edge of the DCLK. The DCLK cannot be used as the internal clock for other functions of
the display module.
Vertical synchronization (VS) is used to indicate when a new frame of the display is received. This is low
enable and its state is read to the display module by a rising edge of the DCLK signal.
Horizontal synchronization (HS) IS used to indicate when a new line of the frame is received. This is low
enable and its state is read to the display module by a rising edge of the DCLK signal.
Data Enable (DE) is used to indicate when the RGB information that should be transferred in the display is
received. This is a high enable, and its state is read to the display module by a rising edge of the DCLK signal.
D[17:0] is used to indicate what is the information of the image that is transferred on the display (when DE = 0
(low) and there is a rising edge of DCLK). D[17:0] can be 0(low) or 1(high). These lines are read by a rising
edge of the DCLK signal. In RGB interface modes, the input display data is written to GRAM first then outputs
the corresponding source voltage according to the gray data from GRAM.
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4.4.3 DPI(RGB) Interface timing
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4.5 Power ON/OFF Sequence
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IOVDD and VDD can be applied or powered down in any order. During the Power Off sequence ,if the LCD is
in the Sleep In mode, VDD and IOVDD must be powered down with a minimum of 120 msec.If the LCD is in
the Sleep In mode, VDD and IOVDD can be powered down with a minimum of 0msec after the /RST has
been released. /CS can be applied at any time or can be permanently grounded. /RST has priority over /CS.
Notes:
1. There will be no damage to the ILI9488 if the power sequences are not met.
2. There will be no abnormal visible effects on the display panel during the Power On/Off Sequence.
3. There will be no abnormal visible effects on the display between the end of the Power On Sequence and before receiving the Sleep
Out command, and also between receiving the Sleep In command and the Power Off Sequence.
4. If the /RST line is not steadily held by the host during the Power On Sequence as defined in Sections 11.1 and 11.2 ( ILI9488
datasheet ), then it will be necessary to apply the Hardware /RST after the completion of the Host Power On Sequence to ensure
correct operations. Otherwise, all the functions are not guaranteed.
5. When the power is turned on, the climb period timing (Trise) must be greater than 10us.
6. Keep data pins D[17:0] at low level, or IOVDD comes later
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4.6 Reset timing
Item
Symbol
MIN.
TYP.
MAX.
Unit
Reset LOW pulse width
t RW
1.0
-
-
us
Reset time
T RT
-
-
120
ms
5 . Optical Characteristics
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6. Design and Handling Precaution
Please refer to "LCD-Module-Design-Handling-Precaution.pdf".
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